VHDL IMPLEMENTATION OF 100 BASE-T4 NETWORK REPEATER

Abstract

100BASE-T4 was an early implementation of Fast Ethernet standards that carry traffic at the nominal rate of 100 Mbit/s, against the original Ethernet speed of 10 Mbit/s. 100BaseT4 started in the IEEE 802.3u committee as Fast Ethernet. It requires four twisted copper pairs, One pair is reserved for transmit, one for receive, and the remaining two will switch direction. The function of the network repeater is to create the logical equivalent of a shared medium. Each host on the network connects to a common repeater through a segment of twisted pair coaxial cable. The repeater logically joins cable segments to create a larger network. They improve reliability and performance because they isolate hosts with faulty connections and prevent them from disrupting the rest of the network to summarize the functions of the repeater.

100 Base T4 network repeater receives data from One port and retransmits it to the other ports It detects collisions, activity, and errors, generating and transmitting the appropriate symbols under these conditions and it detects, jabbering and partition conditions, asserting tx_en, rx_en as appropriate. To accomplish the functions required of the network repeater, the incoming data must be buffered and the correct symbols generated. The buffered data must be multiplexed with other symbols, depending on which data should be transmitted to the active ports.

The complete design is going to be coded using VHDL, then functional simulation will be performed using ISE SIMULATOR; the design will be synthesized using XILINX ISE.

Hardware Language: VHDL

Software Tools: Xilinx 9.2i.

Ethernet is based on the idea that a network between a group of computers should behave as a shared medium. Only one host can transmit data at a time, but more than one host may attempt to transmit data at the same time. If a host wishes to transmit data, it must wait until it detects that the medium is not in use. If two hosts transmit at the same time, a collision occurs and both hosts must stop transmission and try to resend their data after an arbitrary waiting period. This technique is a primary feature of Ethernet and is called carrier sense, multiple access with collision detect (CSMA/CD).

The function of the network repeater is to create the logical equivalent of a shared medium. Each host on the network connects to a common repeater through a segment of twisted pair coaxial cable. The repeater logically joins cable segments to create a larger network. They improve reliability and performance because they isolate hosts with faulty connections and prevent them from disrupting the rest of the network. Ethernet conforms to the IEEE 802.3 standard concerning network media, physical interfaces, signaling, and network access protocol.

        A network repeater's basic function is to retransmit data that is sent from one port to all other ports. Transceivers perform the electrical functions needed for interfacing the host ports to the repeater core logic.

2.1. Introduction

            The invention of the transistor by William B. Shockley, Walter H. Brattain and John Bardeen of Bell Telephone Laboratories was followed by the development of the integrated circuit.  The very first IC emerged at the beginning of 1960 and since that time there have already been four generations of ICs: SSI (small scale integration), MSI (medium scale integration), LSI (large scale integration), and VLSI (very large scale integration). Now we are beginning to see the emergence of the 5^th generation, ULSI (ultra large scale integration). Further miniaturization is still to come and more revolutionary advances in applications of this technology must inevitably occur.

2.2. Design

     

Two approaches to VLSI IC design are philosophically identifiable. In the first called a BOTTOM-UP design as illustrated in fig.2.1, the designers starts at the transistor or at gate level and designs sub-circuits of increasing complexity, which are then interconnected to realize the required functionality. In the second, termed the TOP-DOWN design methodology illustrated in fig.2.2, the designer repeatedly decomposes the system-level specifications into groups and sub groups of similar tasks. The lowest level tasks are ultimately implemented in silicon, either with standard circuits that have been previously designed and tested (often termed standard cells) or with low-level circuits designed to meet the required specifications.

            Several trends in the production of VLSI circuits are readily identifiable.  The most visible is the continual shrinking of the minimum geometrical feature size.  The rate at which the minimum feature size decreases is slowing.  This slowing is partially attributable to inherent physical limitation in the photolithographic process and the rapidly increasing costs associated with very resolution processing equipment.

A trend in increasing speed in digital circuits is readily identifiable.  Some research efforts with GaAs suggest that this material may ultimately supplement silicon at very high frequencies.  GaAs is attractive because of higher electron mobility and because of reduced sensitivity to radiation.  The increase in speed and increase in complexity and direct result fo the reduction in feature size.

            A third trend is the increasing complexity of the circuit functiohn and device count on a die.  The trend is crucial for the development of new markets for ICs.

            A forth trend is towards increasing productivity and an ever growing dependence on the computer in the design process.

            A fifth trend is the continuous shift of where design, production and markets are geographically located.

            A sixth trend is a growing coupling of a specific process and its processing equipment.  As feature sizes shrink and processes becomes more complex, the process is becoming increasingly dependent on the performance of specific pieces of equipment.

2.3. Significance of HDL in VLSI design

Programming languages such as FORTRAN, PASCAL and C were being used to describe computer programs that were sequential in nature.  In digital design fields Hardware Description Languages (HDLs) came into existence.  HDLs allowed the designers to model the concurrency of process found in hardware elements.  HDLs such as Verilog HDL and VHDL became popular.  Both Verilog and VHDL simulators to simulate large digital circuits quickly gained acceptance.

            Even though HDLs were popular for logic verification, designers had to translate the HDL-based design into a schematic circuit with interconnection between gates.  The advent of logic synthesis in the design, digital circuits could be described at a Register Transfer Level (RTL) by use of a HDL.  Thus the designer had to specify how the data flows between registers and how the design processes the data.  Logic synthesis tools from the RTL-description automatically extracted the details of gates and their interconnections to implement the circuit.

            Designers no longer had to manually place gates to build digital circuits.  They could describe complex circuits at an abstract level in terms of functionally and dataflow by designing those circuits in HDLs.  Logic synthesis tools would implement the specified functionally in terms of gates and gate interconnections.  HDLs also began to be used for system level design.  HDLs were used for simulation of system boards, interconnects buses, FPGA s and PLA s.

HDLs have many advantages compared to traditional schematic based design.

a)      Designs can be described at a very high abstract level by the use of HDLs.  Designers can write their RTL description without choosing a specific fabrication technology.  Logic synthesis tools can automatically convert the design to any fabrication technology.  If a new technology emerges, designers do not need to redesign the circuit.  They simply input the RTL description to the logic synthesis tool and create new gate-level net list, using the new fabrication technology.

b)     The logic synthesis tool will optimize the circuit in area and timing for the new technology.

c)      By describing designs in HDLs, functional verification of the design can be done early in the design cycle.  Since designers work at the RTL level, they can optimize and modify the RTL description until it meets the desired functionality.   Most design bugs are eliminated at this point.  This cuts down design cycle time significantly because the probability of hitting a functional bug at a later time in the gate-level net list or physical layout is minimized.

d)     Designing with HDLs is analogous to computer programming.  A textual description with comments is an easier way to develop and debug circuits.  This also provides a concise representation of  the design, compared to gate level schematics.  Gate level schematics are almost incomprehensible of very complex designs.

HDLs are most certainly a trend of the future.  With rapidly increasing complexities of digital circuits and increasingly sophisticated CAD tools, HDLs will probably be the only method for large digital designs.  No digital circuit designer can afford to ignore HDL-based design.

2.4. VHDL

2.4.1. Introduction to VHDL

VHDL stands for “VHSIC Hardware Description Language.” VHSIC, in turn stands for “Very High Speed Integrated Circuit”. The word 'hardware', however, is used in a wide variety of contexts which range from complete systems like personal computers on one side to the small logical gates on their internal integrated circuits on the other side.

This is why different descriptions exist for the hardware functionality. Complex systems are often described by the behavior that is observable from the outside. The description of a basic logic gate, on the other hand, may consist of only one Boolean equation. This is a very short and precise description. The language VHDL covers the complete range of applications and can be used to model (digital) hardware in a general way.

Hardware Description Language (HDL) = "Programming"-language for modeling of (digital) hardware

2.4.2. History

VHDL is a language which is permanently extended and revised. The original standard itself needed more than 16 years from the initial concept to the final, official IEEE standard. When the document passed the committee it was agreed that the standard should be revised every 5 years. The first revision phase resulted in the updated standard of the year1993.

Independently of this revision agreement, additional effort is made to standardize "extensions" of the pure language reference. These extensions cover for examples packages (std_logic_1164, numeric_bit, numeric_std ...) containing widely needed data types and subprograms, or the definition of special VHDL subsets like the synthesis subset IEEE 1076.6.

The latest extension is the addition of analogue description mechanisms to the standard which results in a VHDL superset called VHDL-AMS.

VHDL development was initiated originally from the American Department of Defense (DoD). They requested a language for describing a hardware, which had to be readable for machines and humans at the same time and strictly forces the developer to write structured and comprehensible code, so that the source code itself can serve as a kind of specification document. Most important was the concept of concurrency to cope with the parallelism of digital hardware. Sequential statements to model very complex functions in a compact form were also allowed.
           

In 1987, VHDL was standardized by the American Institute of Electrical and Electronics Engineers (IEEE) for the first time with the first official update in 1993. Apart from the file handling procedures these two versions of the standard are compatible. The standard of the language is described in the Language Reference Manual (LRM).

A new and difficult stage was entered with the effort to upgrade VHDL with analogue and mixed-signal language elements. The upgrade is called VHDL-AMS (analogue- mixed- signal) and it is a superset of VHDL. The digital mechanisms and methods have not been altered by the extension.

For the time being, only simulation is feasible for the analogue part because analogue synthesis is a very complex problem affected by many boundary conditions. The mixed signal simulation has to deal with the problem of synchronizing the digital- and analogue simulators, which has not been solved adequately.

2.4.3. Features of VHDL

The VHDL Hardware Description Language has the following features

• Designs may be decomposed hierarchically.
• Each Design element has both a well-defined interface (for connecting it to other elements) and a precise behavioral specification (for simulating it).
• Behavioral specifications can use either an algorithm or an actual hardware structure to define an element’s operation.  For example, an element can be defined initially by an algorithm, to allow design verification of higher level elements that use it; later, the algorithmic definition can be replaced by a hardware structure.
• Concurrency, timing, and clocking can all be modeled.  VHDL handles asynchronous as well as synchronous sequential-circuit structures.
• The logical operation and timing behavior of a design can be simulated.

Ethernet is a family of frame-based computer networking technologies for local area networks (LANs). The name comes from the physical concept of the ether. It defines a number of wiring and signaling standards for the Physical Layer of the OSI networking model, through means of network access at the Media Access Control (MAC) /Data Link Layer, and a common addressing format.

Ethernet is based on the idea that a network between a group of computers should behave as a shared medium. Only one host can transmit data at a time, but more than one host may attempt to transmit data at the same time. If a host wishes to transmit data, it must wait until it detects that the medium is not in use. If two hosts transmit at the same time, a collision occurs and both hosts must stop transmission and try to resend their data after an arbitrary waiting period. This technique is a primary feature of Ethernet and is called carrier sense, multiple access with collision detect (CSMA/CD).

The function of the network repeater is to create the logical equivalent of a shared medium. Each host on the network connects to a common repeater through a segment of twisted pair coaxial cable. The repeater logically joins cable segments to create a larger network. They improve reliability and performance because they isolate hosts with faulty connections and prevent them from disrupting the rest of the network. Ethernet conforms to the IEEE 802.3 standard concerning network media, physical interfaces, signaling, and network access protocol.

Ethernet is standardized as IEEE 802.3. The combination of the twisted pair versions of Ethernet for connecting end systems to the network, along with the fiber optic versions for site backbones, is the most widespread wired LAN technology. It has been in use from around 1980^[1] to the present, largely replacing competing LAN standards such as token ring, FDDI, and ARCNET.

Ethernet was originally developed at Xerox PARC in 1973–1975. In 1975, Xerox filed a patent application listing Robert Metcalfe and David Boggs, plus Chuck Thacker and Butler Lampson, as inventors (U.S. Patent 4,063,220 : Multipoint data communication system with collision detection). In 1976, after the system was deployed at PARC, Metcalfe and Boggs published a seminal paper.

The experimental Ethernet described in that paper ran at 3 Mbit/s, and had 8-bit destination and source address fields, so the original Ethernet addresses were not the MAC addresses they are today. By software convention, the 16 bits after the destination and source address fields were a packet type field, but, as the paper says, "different protocols use disjoint sets of packet types", so those were packet types within a given protocol, rather than the packet type in current Ethernet which specifies the protocol being used.

Metcalfe left Xerox in 1979 to promote the use of personal computers and local area networks (LANs), forming 3Com. He convinced DEC, Intel, and Xerox to work together to promote Ethernet as a standard, the so-called "DIX" standard, for "Digital/Intel/Xerox"; it standardized the 10 megabits/second Ethernet, with 48-bit destination and source addresses and a global 16-bit type field. The standard was first published on September 30, 1980. It competed with two largely proprietary systems, token ring and ARCNET, but those soon found themselves buried under a tidal wave of Ethernet products. In the process, 3Com became a major company.

3.1. Description

Twisted-pair Ethernet systems have been developed since the mid-80s, beginning with StarLAN, but becoming widely known with 10BASE-T. These systems replaced the coaxial cable on which early Ethernets were deployed with a system of hubs linked with unshielded twisted pair (UTP), ultimately replacing the CSMA/CD scheme in favor of a switched full duplex system offering higher performance.

Ethernet was originally based on the idea of computers communicating over a shared coaxial cable acting as a broadcast transmission medium. The methods used show some similarities to radio systems, although there are fundamental differences, such as the fact that it is much easier to detect collisions in a cable broadcast system than a radio broadcast. The common cable providing the communication channel was likened to the ether and it was from this reference that the name "Ethernet" was derived.

From this early and comparatively simple concept, Ethernet evolved into the complex networking technology that today underlies most LANs. The coaxial cable was replaced with point-to-point links connected by Ethernet hubs and/or switches to reduce installation costs, increase reliability, and enable point-to-point management and troubleshooting. StarLAN was the first step in the evolution of Ethernet from a coaxial cable bus to a hub-managed, twisted-pair network. The advent of twisted-pair wiring dramatically lowered installation costs relative to competing technologies, including the older Ethernet technologies.

Above the physical layer, Ethernet stations communicate by sending each other data packets, blocks of data that are individually sent and delivered. As with other IEEE 802 LANs, each Ethernet station is given a single 48-bit MAC address, which is used both to specify the destination and the source of each data packet. Network interface cards (NICs) or chips normally do not accept packets addressed to other Ethernet stations. Adapters generally come programmed with a globally unique address, but this can be overridden, either to avoid an address change when an adapter is replaced, or to use locally administered addresses.

Despite the significant changes in Ethernet from a thick coaxial cable bus running at 10 Mbit/s to point-to-point links running at 1 Gbit/s and beyond, all generations of Ethernet (excluding early experimental versions) share the same frame formats (and hence the same interface for higher layers), and can be readily interconnected.

Due to the ubiquity of Ethernet, the ever-decreasing cost of the hardware needed to support it, and the reduced panel space needed by twisted pair Ethernet, most manufacturers now build the functionality of an Ethernet card directly into PC motherboards, obviating the need for installation of a separate network card.

CSMA/CD shared medium Ethernet

Ethernet originally used a shared coaxial cable (the shared medium) winding around a building or campus to every attached machine. A scheme known as carrier sense multiple access with collision detection (CSMA/CD) governed the way the computers shared the channel. This scheme was simpler than the competing token ring or token bus technologies. When a computer wanted to send some information, it used the following algorithm.

Main procedure

1. Frame ready for transmission.
2. Is medium idle? If not, wait until it becomes ready and wait the interframe gap period (9.6 µs in 10 Mbit/s Ethernet).
3. Start transmitting.
4. Did a collision occur? If so, go to collision detected procedure.
5. Reset retransmission counters and end frame transmission.

Collision detected procedure

1. Continue transmission until minimum packet time is reached (jam signal) to ensure that all receivers detect the collision.
2. Increment retransmission counter.
3. Was the maximum number of transmission attempts reached? If so, abort transmission.
4. Calculate and wait random back off period based on number of collision
5. Re-enter main procedure at stage 1.

This can be likened to what happens at a dinner party, where all the guests talk to each other through a common medium (the air). Before speaking, each guest politely waits for the current speaker to finish. If two guests start speaking at the same time, both stop and wait for short, random periods of time (in Ethernet, this time is generally measured in microseconds). The hope is that by each choosing a random period of time, both guests will not choose the same time to try to speak again, thus avoiding another collision. Exponentially increasing back-off times (determined using the truncated binary exponential backoff algorithm) are used when there is more than one failed attempt to transmit.

Computers were connected to an Attachment Unit Interface (AUI) transceiver, which was in turn connected to the cable (later with thin Ethernet the transceiver was integrated into the network adapter). While a simple passive wire was highly reliable for small Ethernets, it was not reliable for large extended networks, where damage to the wire in a single place, or a single bad connector, could make the whole Ethernet segment unusable. Multipoint systems are also prone to very strange failure modes when an electrical discontinuity reflects the signal in such a manner that some nodes would work properly while others work slowly because of excessive retries or not at all (see standing wave for an explanation of why); these could be much more painful to diagnose than a complete failure of the segment. Debugging such failures often involved several people crawling around wiggling connectors while others watched the displays of computers running a ping command and shouted out reports as performance changed.

Since all communications happen on the same wire, any information sent by one computer is received by all, even if that information is intended for just one destination. The network interface card interrupts the CPU only when applicable packets are received: the card ignores information not addressed to it unless it is put into "promiscuous mode". This "one speaks, all listen" property is a security weakness of shared-medium Ethernet, since a node on an Ethernet network can eavesdrop on all traffic on the wire if it so chooses. Use of a single cable also means that the bandwidth is shared, so that network traffic can slow to a crawl when, for example, the network and nodes restart after a power failure.

3.3. Data Frame Structure

The frame format is given as follows

Ethernet AMC data frame

• Preamble - used by the receiving hosts to detect the presence of a carrier and initiate clock recovery (7 bytes, equal to " 1010..." for PLL synchronization)

• Start of frame delimiter (SFD) - indicates to the receiving hosts that the next group of bits is the actual data to be transmitted (1 byte)

• Destination address - 48-bit address that uniquely identifies which host on the network

should receive the frame. A host address is created by taking the 24-bit organizationally

unique identifier (OUI) assigned to each organization. The remaining 24 bits are determined internally by network administrators.

• Source address - a 48-bit address that uniquely identifies which host is sending the frame.

• Length - a 2-byte field that determines how many bytes of data are in the data field.

• Data - the minimum data field size is 46 bytes. If fewer than 46 bytes of data need to be sent, additional (pad) characters are added to the end of the data field. The maximum data field size is 1,500 bytes.

• Frame check sequence (FCS) - the FCS is a 32-bit cyclic redundancy check (CRC) computed from a standard CRC polynomial. The receiving host computes a CRC from the bits it receives and compares the value to the FCS imbedded in the frame to see whether the data was received error free.

In order to transmit 100 Mb/s over 4 pairs, the frequency of operation must be 25 MHz. The repeater does not check the frame size of frames sent by nodes. It only retransmits the data.

Protocol

When the carrier sense (crs) signal is received from any port, the repeater must buffer the incoming data frame and retransmit the frame to all other functional ports if the following conditions hold true:

• there is not a collision

• the port is not jabbering

• the port is not partitioned

A collision occurs when more than one carrier sense becomes active. In the case of a collision, a jam symbol must be generated and transmitted to all ports, including the one previously sending data. The ports that caused the collision will then wait for an arbitrary length of time before attempting to resend data across the network. A port is jabbering if it continually transmits data for 40,000 to 75,000 bit times. If a port is jabbering, the repeater will stop receiving data from this port by inhibiting rx_en. This will free up the network for other ports to send data. The port will be considered to have ceased jabbering after carrier sense is deasserted.

A port is partitioned from the network if it causes 60 or more consecutive collisions. This action is necessary because continued collisions will bring all network communication to a halt. A large number of consecutive collisions can often be attributed to a broken cable or faulty connection. A partitioned port is reconnected if activity on another port occurs for 450 to 560 bit times without the assertion of carrier sense from the partitioned port.

If carrier sense is not asserted by any of the ports, then idle symbols are generated and transmitted on all ports. If rx_er is asserted by a receiving port while the repeater is retransmitting data to the other ports, then bad symbols are generated and transmitted to all other ports until crs is deasserted or there is a collision. To summarize, the repeater receives data from one port and transmits to all other ports. The repeater detects collisions, activity, and errors, and generates the appropriate symbols under these conditions. It also detects jabbering and partition conditions, and asserts tx_en (transmit enable) and rx_en (receive enable) when appropriate.

3.4. Repeaters and hubs

For signal degradation and timing reasons, coaxial Ethernet segments had a restricted size which depended on the medium used. For example, 10BASE5 coax cables had a maximum length of 500 meters (1,640 ft). Also, as was the case with most other high-speed buses, Ethernet segments had to be terminated with a resistor at each end. For coaxial-cable-based Ethernet, each end of the cable had a 50-ohm resistor attached. Typically this resistor was built into a male BNC or N connector and attached to the last device on the bus, or, if vampire taps were in use, to the end of the cable just past the last device. If termination was not done, or if there was a break in the cable, the AC signal on the bus was reflected, rather than dissipated, when it reached the end. This reflected signal was indistinguishable from a collision, and so no communication would be able to take place.

A greater length could be obtained by an Ethernet repeater, which took the signal from one Ethernet cable and repeated it onto another cable. If a collision was detected, the repeater transmitted a jam signal onto all ports to ensure collision detection. Repeaters could be used to connect segments such that there were up to five Ethernet segments between any two hosts, three of which could have attached devices. Repeaters could detect an improperly terminated link from the continuous collisions and stop forwarding data from it. Hence they alleviated the problem of cable breakages: when an Ethernet coax segment broke, while all devices on that segment were unable to communicate, repeaters allowed the other segments to continue working - although depending on which segment was broken and the layout of the network the partitioning that resulted may have made other segments unable to reach important servers and thus effectively useless.

People recognized the advantages of cabling in a star topology, primarily that only faults at the star point will result in a badly partitioned network, and network vendors started creating repeaters having multiple ports, thus reducing the number of repeaters required at the star point. Multiport Ethernet repeaters became known as "Ethernet hubs". Network vendors such as DEC and SynOptics sold hubs that connected many 10BASE2 thin coaxial segments. There were also "multi-port transceivers" or "fan-outs". These could be connected to each other and/or a coax backbone. The best-known early example was DEC's DELNI. These devices allowed multiple hosts with AUI connections to share a single transceiver. They also allowed creation of a small standalone Ethernet segment without using a coaxial cable. A twisted pair CAT-3 or CAT-5 cable is used to connect 10BASE-T Ethernet

Ethernet on unshielded twisted-pair cables (UTP), beginning with StarLAN and continuing with 10BASE-T, was designed for point-to-point links only and all termination was built into the device. This changed hubs from a specialist device used at the center of large networks to a device that every twisted pair-based network with more than two machines had to use. The tree structure that resulted from this made Ethernet networks more reliable by preventing faults with (but not deliberate misbehavior of) one peer or its associated cable from affecting other devices on the network, although a failure of a hub or an inter-hub link could still affect lots of users. Also, since twisted pair Ethernet is point-to-point and terminated inside the hardware, the total empty panel space required around a port is much reduced, making it easier to design hubs with lots of ports and to integrate Ethernet onto computer motherboards.

Despite the physical star topology, hubbed Ethernet networks still use half-duplex and CSMA/CD, with only minimal activity by the hub, primarily the Collision Enforcement signal, in dealing with packet collisions. Every packet is sent to every port on the hub, so bandwidth and security problems aren't addressed. The total throughput of the hub is limited to that of a single link and all links must operate at the same speed.

Collisions reduce throughput by their very nature. In the worst case, when there are lots of hosts with long cables that attempt to transmit many short frames, excessive collisions can reduce throughput dramatically. However, a Xerox report in 1980 summarized the results of having 20 fast nodes attempting to transmit packets of various sizes as quickly as possible on the same Ethernet segment.^[4] The results showed that, even for the smallest Ethernet frames (64B), 90% throughput on the LAN was the norm. This is in comparison with token passing LANs (token ring, token bus), all of which suffer throughput degradation as each new node comes into the LAN, due to token waits.

This report was wildly controversial, as modeling showed that collision-based networks became unstable under loads as low as 40% of nominal capacity. Many early researchers failed to understand the subtleties of the CSMA/CD protocol and how important it was to get the details right, and were really modeling somewhat different networks (usually not as good as real Ethernet).

3.5. Bridging and switching

While repeaters could isolate some aspects of Ethernet segments, such as cable breakages, they still forwarded all traffic to all Ethernet devices. This created practical limits on how many machines could communicate on an Ethernet network. Also as the entire network was one collision domain and all hosts had to be able to detect collisions anywhere on the network, and the number of repeaters between the farthest nodes was limited. Finally segments joined by repeaters had to all operate at the same speed, making phased-in upgrades impossible.

To alleviate these problems, bridging was created to communicate at the data link layer while isolating the physical layer. With bridging, only well-formed packets are forwarded from one Ethernet segment to another; collisions and packet errors are isolated. Bridges learn where devices are, by watching MAC addresses, and do not forward packets across segments when they know the destination address is not located in that direction.

Prior to discovery of network devices on the different segments, Ethernet bridges and switches work somewhat like Ethernet hubs, passing all traffic between segments. However, as the switch discovers the addresses associated with each port, it only forwards network traffic to the necessary segments, improving overall performance. Broadcast traffic is still forwarded to all network segments. Bridges also overcame the limits on total segments between two hosts and allowed the mixing of speeds, both of which became very important with the introduction of Fast Ethernet.

Early bridges examined each packet one by one using software on a CPU, and some of them were significantly slower than hubs (multi-port repeaters) at forwarding traffic, especially when handling many ports at the same time. This was in part due to the fact that the entire Ethernet packet would be read into a buffer, the destination address compared with an internal table of known MAC addresses and a decision made as to whether to drop the packet or forward it to another or all segments.

In 1989 the networking company Kalpana introduced their EtherSwitch, the first Ethernet switch. This worked somewhat differently from an Ethernet bridge, in that only the header of the incoming packet would be examined before it was either dropped or forwarded to another segment. This greatly cut down the forwarding latency and the processing load at a stroke, revolutionising Ethernet. One drawback of this cut-through switching method was that packets that had been corrupted at a point beyond the header could still be propagated through the network, so a jabbering station could continue to disrupt the entire network. The remedy for this was to make available store-and-forward switching, where the packet would be read into a buffer on the switch in its entirety, verified against its checksum and then forwarded. This was essentially a return to the orginal approach of bridging, but with the advantage of more powerful, application-specific processors being used. Hence the bridging is then done in hardware, allowing packets to be forwarded at full wire speed. It is important to remember that the term switch was invented by device manufacturers and does not appear in the 802.3 standard.

Since packets are typically only delivered to the port they are intended for, traffic on a switched Ethernet is slightly less public than on shared-medium Ethernet. Despite this, switched Ethernet should still be regarded as an insecure network technology, because it is easy to subvert switched Ethernet systems by means such as ARP spoofing and MAC flooding. The bandwidth advantages, the slightly better isolation of devices from each other, the ability to easily mix different speeds of devices and the elimination of the chaining limits inherent in non-switched Ethernet have made switched Ethernet the dominant network technology.

When a twisted pair or fiber link segment is used and neither end is connected to a hub, full-duplex Ethernet becomes possible over that segment. In full duplex mode both devices can transmit and receive to/from each other at the same time, and there is no collision domain. This doubles the aggregate bandwidth of the link and is sometimes advertised as double the link speed (e.g. 200 Mbit/s) to account for this. However, this is misleading as performance will only double if traffic patterns are symmetrical (which in reality they rarely are). The elimination of the collision domain also means that all the link's bandwidth can be used and that segment length is not limited by the need for correct collision detection (this is most significant with some of the fiber variants of Ethernet).

3.6. Fast Ethernet

• 100BASE-T: A term for any of the three standard for 100 Mbit/s Ethernet over twisted pair cable. Includes 100BASE-TX, 100BASE-T4 and 100BASE-T2.
• 100BASE-TX: Uses two pairs, but requires Category 5 cable. Similar star-shaped configuration to 10BASE-T. 100 Mbit/s.
• 100BASE-T4: 100 Mbit/s Ethernet over Category 3 cabling (as used for 10BASE-T installations). Uses all four pairs in the cable. Now obsolete, as Category 5 cabling is the norm. Limited to half-duplex.
• 100BASE-T2: No products exist. 100 Mbit/s Ethernet over Category 3 cabling. Supports full-duplex, and uses only two pairs. It is functionally equivalent to 100BASE-TX, but supports old cable.
• 100BASE-FX: 100 Mbit/s Ethernet over fibre.

Gigabit Ethernet

• 1000BASE-T: 1 Gbit/s over Category 5e copper cabling.
• 1000BASE-SX: 1 Gbit/s over fiber.
• 1000BASE-LX: 1 Gbit/s over fiber. Optimized for longer distances over single-mode fiber.
• 1000BASE-CX: A short-haul solution (up to 25 m) for running 1 Gbit/s Ethernet over special copper cable. Predates 1000BASE-T, and now obsolete.

10-gigabit Ethernet

The 10-gigabit Ethernet family of standards encompasses media types for single-mode fibre (long haul), multi-mode fibre (up to 300 m), copper backplane (up to 1 m) and copper twisted pair (up to 100 m). It was first standardised as IEEE Std 802.3ae-2002, but is now included in IEEE Std 802.3-2008.

• 10GBASE-SR: designed to support short distances over deployed multi-mode fiber cabling, it has a range of between 26 m and 82 m depending on cable type. It also supports 300 m operation over a new 2000 MHz·km multi-mode fiber.
• 10GBASE-LX4: uses wavelength division multiplexing to support ranges of between 240 m and 300 m over deployed multi-mode cabling. Also supports 10 km over single-mode fiber.
• 10GBASE-LR and 10GBASE-ER: these standards support 10 km and 40 km respectively over single-mode fiber.
• 10GBASE-SW, 10GBASE-LW and 10GBASE-EW. These varieties use the WAN PHY, designed to interoperate with OC-192 / STM-64 SONET/SDH equipment. They correspond at the physical layer to 10GBASE-SR, 10GBASE-LR and 10GBASE-ER respectively, and hence use the same types of fiber and support the same distances. (There is no WAN PHY standard corresponding to 10GBASE-LX4.)
• 10GBASE-T: designed to support copper twisted pair was specified by the IEEE Std 802.3an-2006 which has been incorporated into the IEEE Std 802.3-2008.

Ten-gigabit Ethernet is still an emerging technology, and it remains to be seen which of the standards will gain commercial acceptance.

The functions of the repeater are:

1) In general, the repeater receives data from one port and retransmits it to the other ports;

2) it detects collisions, activity, and errors, generating and transmitting the appropriate symbols under these conditions; and

3) it detects jabbering and partition conditions, asserting tx_en, rx_en as appropriate. To accomplish the functions required of the network repeater, the incoming data must be buffered and the correct symbols generated. The buffered data must be multiplexed with other symbols, depending on which data should be transmitted to the active ports.  

WLANs offer tremendous convenience but a drawback of these systems is the limited area covered by WiFi signals. Obstructions and other common electronic devices interfere with and degrade signal strength. This can make it difficult to connect from a basement, back room, or upstairs office, depending on placement of the wireless router and other variables. A wireless network repeater can be the answer.

A WiFi network repeater will pick up the signal from a wireless router and amplify it, propagating signal strength to boost distance and coverage of the WLAN. For example, assume an upstairs office gets only a weak signal from a router located in the basement. The building might have a steel infrastructure, cordless phones and other forms of interference.

Another option is to setup a network repeater on the lower floor, halfway between the basement and the upstairs office. The repeater should magnify the signal enough to get good coverage in the upstairs floor. If the building is quite large, several network repeaters can be placed strategically to “draw” the signal where required, though this concept has its limits. Devices communicating with an intermediate network repeater will have lower performance stats than those communicating directly with the router. This becomes more of an issue as additional repeaters are used in line.

Additionally, there are two types of repeaters available: those with an external antenna and those with an internal antenna. The former plugs into an electrical outlet and is less obvious. The latter sits out on a desk or table. In this case, a removable hybrid antenna is desirable over a fixed antenna, while some models feature two antennas. Other repeaters allow an external antenna to be connected, which can be advantageous when attempting to cover a large building.

The basic objectives for a repeater are to:

• Detect carrier activity on ports and receive Ethernet frames on active ports

• Restore the shape, amplitude, and timing of the received frame signals prior to retransmission

• Forward the Ethernet frame to each of the active ports

• Detect and signal a collision event throughout the network

• Extend a network's physical dimensions

• Protect a network from failures of stations, cables, ports, and so forth

• Allow the installation and removal of stations without network disruption

• Support interoperability of various physical layers (10BASE2, 10BASE-T, etc.)

• Provide centralized management of network operations and statistics

• Provide for low-cost network installation, growth, and maintenance

• Partition bad segments

A network repeater's basic function is to retransmit data that is sent from one port to all other ports. Transceivers perform the electrical functions needed for interfacing the host ports to the repeater core logic. Each transceiver interface provides the following signals to the repeater:

• carrier sense (crs)

• receive clock (rx_clk)

• receive data valid (rx_dv)

• receive data error (rx,_er)

• three pairs of data (rxd0 - rxd5)

The signal crs indicates that data is being received by the transceiver. rx_clk is the clock recovered from the incoming data by the transceiver and is used to synchronize the data, rxd0 - rxd5. The signal rx_dv informs the repeater core that the received data, is valid. It is asserted at the start of a data frame (at the data frame's start of frame delimiter, SFD) and deasserted at the end of a frame. The rx_er signal indicates that an error was detected in the reception of the data.

FIGURE : 5.10

Simulation Results for the Top Module

Conclusion

                  As the use of high performance PCs and servers and high-bandwidth applications increases, the use of high throughput networking grows. The most popular method for high performance PC and server connections is 100 BASE-T Fast Ethernet. Fast Ethernet provides a high performance solution at a low cost and simple integration with 10 BASE-T Ethernet. With broad usage of Fast Ethernet products has come the need to support a broader range of network cabling types.

                                      Thus by using the network repeater noise can be reduced. It is flexible so that we can implement it for 16-bit and 32-bit. The hardware becomes very complex. In this project a 100 base T4 network repeater is implemented using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The proposed work involves study of Spartan-3E FPGA architecture, implementation of several modules in VHDL and finally synthesis on Spartan-3E FPGA 

7.1. VHDL Code

Arbiter

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity arbiter8 is

    Port ( txclk : in  STD_LOGIC;

           areset : in  STD_LOGIC;

           activity1 : in  STD_LOGIC;

           activity2 : in  STD_LOGIC;

           activity3 : in  STD_LOGIC;

           activity4 : in  STD_LOGIC;

           activity5 : in  STD_LOGIC;

           activity6 : in  STD_LOGIC;

           activity7 : in  STD_LOGIC;

           activity8 : in  STD_LOGIC;

           sel1 : buffer  STD_LOGIC;

           sel2 : buffer STD_LOGIC;

           sel3 : buffer  STD_LOGIC;

           sel4 : buffer  STD_LOGIC;

           sel5 : buffer  STD_LOGIC;

           sel6 : buffer  STD_LOGIC;

           sel7 : buffer  STD_LOGIC;

           sel8 : buffer STD_LOGIC;

           nosel : buffer STD_LOGIC;

           carrier :buffer  STD_LOGIC;

           collision : buffer STD_LOGIC);

end arbiter8;

architecture Behavioral of arbiter8 is

signal colin, carin: std_logic;

signal activityin1, activityin2, activityin3, activityin4: std_logic;

signal activityin5, activityin6, activityin7, activityin8: std_logic;

 signal noactivity: std_logic;

 component rdff1 is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           d : in  STD_LOGIC;

           q : buffer  STD_LOGIC);

                        end component;

begin

--Components

            ul: rdff1 port map (txclk, areset, activityin1, sel1) ;

            u2: rdff1 port map (txclk, areset, activityin2, sel2);

            u3: rdff1 port map (txclk, areset, activityin3, sel3) ;

            u4: rdff1 port map (txclk, areset, activityin4, sel4);

            u5: rdff1 port map (txclk, areset, activityin5, sel5) ;

            u6: rdff1 port map (txclk, areset, activityin6, sel6);

            u7: rdff1 port map (txclk, areset, activityin7, sel7) ;

            u8: rdff1 port map (txclk, areset, activityin8, sel8);

            u9: rdff1 port map (txclk, areset, noactivity, nosel);

            ul0: rdff1 port map (txclk, areset, colin, collision);

            ull: rdff1 port map (txclk, areset, carin, carrier) ;

--Arbitration Select Logic

            activityin1 <= activity1;

            activityin2 <= activity2 and not activity1;

            activityin3 <= activity3 and not(activity1 or activity2);

            activityin4 <= activity4 and not(activity1 or activity2 or activity3);

            activityin5 <= activity5 and not(activity1 or activity2 or activity3 or activity4);

            activityin6 <= activity6 and not(activity1 or activity2 or activity3 or activity4 or    activity5);

            activityin7<=  activity7 and not(activity1 or activity2 or activity3 or activity4 or    activity5 or activity6);

            activityin8 <= activity8 and not(activity1 or activity2 or activity3 or activity4 or    activity5 or activity6 or activity7);

            noactivity <= not(activity1 or activity2 or activity3 or activity4 or activity5 or        activity6 or activity7 or activity8);

             colin<= (activity1 and (activity2 or activity3 or activity4 or activity5 or activity6 or activity7 or activity8)) or

            (activity2 and (activity1 or activity3 or activity4

             or activity5 or activity6 or activity7 or activity8)) or

                                    (activity3 and (activity1 or activity2 or activity4

                                    or activity5 or activity6 or activity7 or activity8)) or

                                    (activity4 and (activity1 or activity2 or activity3

                                    or activity5 or activity6 or activity7 or activity8)) or

                                    (activity5 and (activity1 or activity2 or activity3

                                    or activity4 or activity6 or activity7 or activity8)) or

                                    (activity6 and (activity1 or activity2 or activity3

                                    or activity4 or activity5 or activity7 or activity8)) or

                                    (activity7 and (activity1 or activity2 or activity3

                                    or activity4 or activity5 or activity6 or activity8)) or

                                    (activity8 and (activity1 or activity2 or activity3

                                    or activity4 or activity5 or activity6 or activity7));

                                    carin <= activity1 or activity2 or activity3 or activity4

                                    or activity5 or activity6 or activity7 or activity8 ;

end Behavioral;

Ascount

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ascount is

generic(countersize:integer:=2);

    Port ( clk : in  STD_LOGIC;

           areset : in  STD_LOGIC;

           sreset : in  STD_LOGIC;

           enable : in  STD_LOGIC;

           count : buffer  STD_LOGIC_vector(countersize-1 downto 0));

end ascount;

architecture Behavioral of ascount is

begin

p1: process (areset,clk,sreset) begin

         if(areset='1') then

                                    count<=(others=>'0');

                                    elsif(clk'event and clk='1') then

                                    if(sreset='1') then

                                    count<=(others=> '0');

                                    elsif enable ='1' then

                                    count<=count+1;

                                    else

                                    count<=count;

                                    end if;

                                    end if;

                                    end process;

end Behavioral;

Clk_Mux

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity clk_mux is

    Port (

           clk1 : in  STD_LOGIC;

           clk2 : in  STD_LOGIC;

           clk3 : in  STD_LOGIC;

           clk4 : in  STD_LOGIC;

           clk5 : in  STD_LOGIC;

           clk6 : in  STD_LOGIC;

           clk7 : in  STD_LOGIC;

           clk8 : in  STD_LOGIC;

           clk9: in std_logic;         

              sel1 : in  STD_LOGIC;

           sel2 : in  STD_LOGIC;

           sel3 : in  STD_LOGIC;

           sel4 : in  STD_LOGIC;

           sel5 : in  STD_LOGIC;

           sel6 : in  STD_LOGIC;

           sel7 : in  STD_LOGIC;

           sel8 : in  STD_LOGIC;

  sel9: in             std_logic;

           rxclk : buffer  STD_LOGIC);               

end clk_mux;

architecture Behavioral of clk_mux is

signal sel : std_logic_vector(8 downto 0);

begin

            sel<= (sel9,sel8,sel7,sel6,sel5,sel4,sel3,sel2,sel1);

                                                with sel select

                                    rxclk  <=

                                                                                                clk1 when "000000001",

                                                                                                clk2 when "000000010",

                                                                                                clk3 when "000000100",

                                                                                                clk4 when "000001000",

                                                                                                clk5 when "000010000",

                                                                                                clk6 when "000100000",

                                                                                                clk7 when "001000000",

                                                                                                clk8 when "010000000",

                                                                                                clk9 when "100000000",

                                                                                        '0'  when others;

end Behavioral;

Control

library ieee;

use ieee.std_logic_1164.all;

--use basic.regs_pkg.all;

--use basic.synch_pkg.all;

--use basic.counters_pkg.all;

entity control is

            port (txclk: in std_logic;--Reference TX_CLK

                                    areset: in std_logic;--Async reset

                                    carrier: in std_logic;

         collision:in std_logic;

         rx_error: in std_logic;

         rx_dv:  in std_logic;

         symbolendl:in std_logic;

         symbolend2: in std_logic;

         symbolend3: in std_logic;

         symbolclr:buffer std_logic;

         symbolinc:buffer std_logic;

         symbol1:buffer std_logic_vector(1 downto 0);

         symbol2:buffer std_logic_vector(1 downto 0);

                                    symbol3:buffer std_logic_vector(1 downto 0);

                                    switch1: buffer std_logic;

                                    switch2:buffer std_logic;

                                    switch3:buffer std_logic;

                                    wptrclr:buffer std_logic;

                                    wptrinc:buffer std_logic;

                                    rptrclr:buffer std_logic;

                                    rptrinc:buffer std_logic;

                                    txdata:buffer std_logic;

                                    idle:buffer std_logic;

                                    preamble:buffer std_logic;

                                    data:    buffer std_logic;                                

                                    col:  buffer std_logic;

                                    prescale:buffer std_logic);

                                    end control;

architecture behavioral of control is

                        type states1 is (IDLE_STATE1, PRE1_sTATE1, PRE2_sTATE1,                                                               PRE3_sTATE1, DATA_STATE1, JAM_sTATE1,                                                               NOSFD_sTATE1, ERROR_sTATE1);

                                    --attribute state_encoding of statesl:type is one_hot_one;

                        type states2 is (IDLE_sTATE2, PREl_sTATE2, PRE2_sTATE2,                                                                PRE3_sTATE2, DATA_sTATE2, JAM_sTATE2,                                                                NOsFD_sTATE2, ERROR_STATE2, PRE4_sTATE2);

                                    --attribute state_encoding of states2:type is one_hot_one;

                        type states3 is (IDLE_sTATE3, PRE1_sTATE3, PRE2_sTATE3,                                                               PRE3_sTATE3,DATA_STATE3, JAM_STATE3,                                                               NOsFD_sTATE3, ERROR_sTATE3);

                                    --attribute state_encoding of states3:type is one_hot_one;

            signal state1, newstate1: states1;

            signal state2, newstate2: states2;

            signal state3, newstate3: states3;

            signal carrierd, carrierdd: std_logic;

            signal error, rx_dv_in, rx_error_in: std_logic;

            signal no_sfd, no_sfd_in, no_data, data_valid: std_logic;

            signal prescale_in: std_logic;

            signal pout: std_logic_vector(9 downto 0);

            constant jam: std_logic_vector(1 downto 0) := "00";

            constant pre: std_logic_vector(1 downto 0) := "00";

            constant sosb: std_logic_vector(1 downto 0) := "01";

            constant bad: std_logic_vector(1 downto 0) :="10";

            constant zero: std_logic_vector(1 downto 0):= "11";

            constant fifodata: std_logic:='1';

            constant symboldata: std_logic :='0';

            signal vdd:      std_logic :='1' ;

            signal vss: std_logic :='0';

component ascount is

generic(countersize:integer:=2);

    Port ( clk : in  STD_LOGIC;

           areset : in  STD_LOGIC;

           sreset : in  STD_LOGIC;

           enable : in  STD_LOGIC;

           count : buffer  STD_LOGIC_vector(countersize-1 downto 0));

end component;

component rdff1 is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           d : in  STD_LOGIC;

           q : buffer STD_LOGIC);

end component;

component rsynch is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           d : in  STD_LOGIC;

           q : buffer  STD_LOGIC);

end component;

--Components

begin

                        ul: rsynch port map (txclk, areset, carrier, carrierdd);

                        u3: rsynch port map (txclk, areset, rx_error_in, error);

                        u5: rdff1 port map (txclk, areset, rx_dv_in, data_valid);

                        u7: rdff1 port map (txclk, areset, no_sfd_in, no_data);

                        u8: ascount generic map(10) port map (txclk, areset, vss, vdd, pout);

                        u9: rdff1 port map(txclk, areset, prescale_in, prescale);

                        rx_dv_in  <= carrierdd and rx_dv; -- filter out glitches

                        rx_error_in <= carrierdd and rx_error; -- filter out glitches

                        wptrclr <= not(rx_dv_in and not collision);

                        no_sfd_in <= (no_sfd or no_data) and carrier;

                        prescale_in<= '1' when pout = "1111111111" else '0';

                        wptrinc <= '1' ;

                        rptrinc <= '1';

                        symbolinc <= '1';

--State machine controllers

--State machine controller Line 3

                                    p3: process (carrier, collision, symbolend3, data_valid,                                                                                 error,state3)

                                                begin

                                                case (state3) is

                                                                        when IDLE_STATE3 =>      

                                                                                                symbol3<= zero;

                                                                                                switch3 <= symboldata;

                                                                                                symbolclr <= '1';

                                                                                                rptrclr <= '1';

                                                                                                preamble<= '0';

                                                                                                data <= '0';

                                                                                                no_sfd<= '0';

                                                                                                idle <= '1';

                                                                                                col <= '0';

                                                                                                txdata<= '0';

                                                            if (collision = '1') then

                                                                                    newstate3 <= JAM_STATE3;

                                                            elsif (carrier = '1') then

                                                                                    newstate3 <= PRE1_STATE3;

                                                            else

                                                                                    newstate3 <= IDLE_STATE3;

end if;

                                                            when PRE1_STATE3 =>

                                                            symbol3<= pre;

                                                            switch3 <= symboldata;

                                                            symbolclr <= '0';

                                                            rptrclr <= '1';

                                                            preamble<= '1';

                                                            data <= '0';

                                                            no_sfd<= '0';

                                                            idle <= '0';

                                                            col <= '0';

                                                            txdata<= '1';

                                    if (carrier = '0') then

                                                newstate3 <= IDLE_STATE3;

                                                elsif (collision = '1') then

                                                newstate3 <= JAM_STATE3;

                                                elsif (symbolend3 = '1') then

                                                newstate3 <= PRE2_STATE3;

                                                else

                                                newstate3 <= PRE1_STATE3;

                                                end if;

                                                                        when PRE2_STATE3 =>

                                                                                    symbol3<= pre;

                                                                                    switch3 <= symboldata;

                                                                                    symbolclr <= '0';

                                                                                    rptrclr <= '1';

                                                                                    preamble<= '1';

                                                                                    data <= '0';

                                                                                    no_sfd<= '0';

                                                                                    idle <= '0';

                                                                                    col <= '0';

                                                                                    txdata<= '1';

                                                                        if (carrier = '0') then

                                                                                    newstate3 <= IDLE_STATE3;

                                                                        elsif (collision = '1') then

                                                                                    newstate3 <= JAM_STATE3;

                                                                        elsif (symbolend3 = '1') then

                                                                                    newstate3 <= PRE3_STATE3;

                                                                        else

                                                                                    newstate3 <= PRE2_STATE3;

end if;

                                    when PRE3_STATE3 =>

                                                symbol3<= sosb;

                                                switch3 <= symboldata;

                                                symbolclr <= '0';

                                                rptrclr <= '1';

                                                preamble<= '1';

                                                data <= '0';

                                                no_sfd<= '0';

                                                idle <= '0' ;

                                                col <= '0';

                                                txdata<= '1';

                                    if (carrier = '0') then

                                                            newstate3 <= IDLE_STATE3;

                                    elsif (collision = '1') then

                                                            newstate3 <= JAM_STATE3;

                                    elsif (symbolend3 = '1' and error = '1') then

                                                            newstate3 <= ERROR_STATE3;

                                    elsif (symbolend3 = '1' and data_valid = '0') then

                                                            newstate3 <= NOSFD_STATE3;

                                    elsif (symbolend3 = '1' and data_valid = '1') then

                                                            newstate3 <= DATA_STATE3;

                                    else

                                                            newstate3 <= PRE3_STATE3;

                                    end if;

                                    when DATA_STATE3 =>

                                                            symbol3<= jam;

                                                            switch3 <= fifodata;

                                                            symbolclr <= '0';

                                                            rptrclr <= '0';

                                                            preamble<= '0';

                                                            data <= '1';

                                                            no_sfd<= '0';

                                                            idle <= '0';

                                                            col <= '0';

                                                            txdata<= '1';

                                    if (carrier = '0') then

                                                            newstate3 <= IDLE_STATE3;

                                                                        elsif (collision = '1') then

                                                                                    newstate3 <= JAM_STATE3;

                                                                        elsif (symbolend3 = '1' and error='1') then

                                                                                    newstate3 <= ERROR_STATE3;

                                                                        else

                                                                                    newstate3 <= DATA_STATE3;

                                                                        end if;

                                    when JAM_STATE3 =>

                                                                        symbol3<= jam;

                                                                        switch3 <= symboldata;

                                                                        symbolclr <= '0';

                                                                        rptrclr <= '1';

                                                                        preamble<= '0';

                                                                        data <= '0';

                                                                        no_sfd<= '0';

                                                                        idle <= '0';

                                                                        col <= '1';

                                                                        txdata<= '1';

                                                                        if (carrier = '0') then

                                                                                    newstate3 <= IDLE_STATE3;

                                                                        else

                                                                                    newstate3 <= JAM_STATE3;

                                                                        end if;

                                    when NOSFD_STATE3 =>

                                                                        symbol3<= jam;

                                                                        switch3 <= symboldata;

                                                                        symbolclr <= '0';

                                                                        rptrclr <= '0';

                                                                        preamble<= '0';

                                                                        data <= '1';

                                                                        no_sfd<= '1';

                                                                        idle <= '0';

                                                                        col <= '0';

                                                                        txdata <='1';

                                                                        if (carrier = '0') then

                                                                                    newstate3 <= IDLE_STATE3;

                                                                        elsif (collision = '1') then

                                                                                    newstate3 <= JAM_STATE3;

                                                                        elsif (symbolend3 = '1' and error='1') then

                                                                                    newstate3 <= ERROR_STATE3;

                                                                        else

                                                                                    newstate3 <= NOSFD_STATE3;

end if;

                                    when ERROR_STATE3=>

                                                                        symbol3<= bad;

                                                                        switch3 <= symboldata;

                                                                        symbolclr <= '0';

                                                                        rptrclr <= '0';

                                                                        preamble<= '0';

                                                                        data <= '1';

                                                                        no_sfd <= '0';

                                                                        idle <= '0' ;

                                                                        col <= '0';

                                                                        txdata<= '1';

                                                                        if (carrier = '0') then

                                                                                    newstate3 <= IDLE_STATE3;

                                                                        elsif (collision = '1') then

                                                                                    newstate3 <= JAM_STATE3;

                                                                        else

                                                                                    newstate3 <= ERROR_STATE3;

end if;

end case;

end process;

                        p3clk: process (txclk,areset)

                                                begin

                                                if areset = '1' then

                                                            state3 <= idle_state3;

                                                elsif (txclk'event and txclk='1') then

                                                            state3 <= newstate3;

end if;

end process;

end  behavioral;

FIFO

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--use basic.regs_pkg.all;

--use basic.rreg;

--use basic.counters_pkg.all;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity fifo is

                        port (

                                                rxclk: in std_logic; --from clock mux circuit

                                                txclk: in std_logic; --Reference TX_CLK

                                                areset: in std_logic;-- Asynch reset

                                                sreset: in std_logic; --Synch reset

                                                wptrclr: in std_logic; --FIFO write pointer clear

                                                wptrinc: in std_logic; --FIFO write pointer incr

                                                rptrclr: in std_logic; --FIFO read pointer clear

                                                rptrinc: in std_logic; --FIFO read poi~ter incr

                                                rxd5: in std_logic; --FIFO data input

                                                rxd4: in std_logic;-- FIFO data input

                                                rxd3: in std_logic;-- FIFO d~ta input

                                                rxd2: in std_logic;-- FIFO data input

                                                rxd1: in std_logic; --FIFO data input

                                                rxd0: in std_logic; ---FIFO data input

                                                dmuxout: buffer std_logic_vector(5 downto 0);

                                                ---FIFO mux output

                                                            wptr2 :buffer std_logic;

                                                            wptr1:buffer std_logic;

                                                            wptr0:buffer std_logic;

                                                            rptr2:buffer std_logic;

                                                            rptr1:buffer std_logic;

                                                            rptr0:buffer std_logic);

                        end fifo;

            architecture behavioral of fifo is

            -- signals

            component rreg is

             generic (size:integer:=2);

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           load : in  STD_LOGIC;

           d : in  STD_LOGIC_vector(size-1 downto 0);

           q : buffer STD_LOGIC_vector(size-1 downto 0));

  end component;

            component ascount is

                                    generic(countersize:integer:=2);

                                    Port ( clk : in  STD_LOGIC;

                                                areset : in  STD_LOGIC;

                                                sreset : in  STD_LOGIC;

                                                enable : in  STD_LOGIC;

                                            count : buffer STD_LOGIC_vector(countersize-1 downto 0));

end component;

            signal rptr, wptr: std_logic_vector(2 downto 0);

            signal qout0, qout1, qout2, qout3, qout4, qout5,

                        qout6, qout7, rxd: std_logic_vector(5 downto 0);

            signal en: std_logic_vector(7 downto 0);

begin

--Components

--FIFO array

            u1: rreg generic map (6) port map (rxclk, areset, en(0), rxd, qout0);

            u2: rreg generic map (6) port map (rxclk, areset, en(1), rxd, qout1);

            u3: rreg generic map (6) port map (rxclk, areset, en(2), rxd, qout2);

            u4: rreg generic map (6) port map (rxclk, areset, en(3) , rxd, qout3);

            u5: rreg generic map (6) port map (rxclk, areset, en(4), rxd, qout4);

            u6: rreg generic map (6) port map (rxclk, areset, en(5), rxd, qout5);

            u7: rreg generic map (6) port map (rxclk, areset, en(6), rxd, qout6);

            u8: rreg generic map (6) port map (rxclk, areset, en(7) , rxd, qout7) ;

            --Write pointer

            u10: ascount generic map (3) port map (rxclk, areset, wptrclr, wptrinc, wptr);

            -- Read pointer

            u11: ascount generic map (3) port map (txclk, areset, rptrclr, rptrinc, rptr);

                                    rxd <= (rxd5, rxd4, rxd3, rxd2, rxd1, rxd0);

                                    wptr2 <= wptr(2);

                                    wptr1 <= wptr(1);

                                    wptr0 <= wptr(0);

                                    rptr2 <= rptr(2);

                                    rptr1 <= rptr(1);

                                    rptr0 <= rptr(0);

                                    --8:1 Data: mux with rptr select

                                                with rptr select

                                                dmuxout <=

                                                                                                qout0 when "000",

                                                                                                qout1 when "001",

                                                                                                qout2 when "010",

                                                                                                qout3 when "011",

                                                                                                qout4 when "100",

                                                                                                qout5 when "101",

                                                                                                qout6 when "110",

                                                                                                qout7 when others;

                        --FIFO register selector decoder (wptr)

                        with wptr select

                                                            en <=

                                                                        "00000001" when "000",

                                                                        "00000010" when "001",

                                                                        "00000100" when "010",

                                                                        "00001000" when "011",

                                                                        "00010000" when "100",

                                                                        "00100000" when "101",

                                                                        "01000000" when "110",

                                                                        "10000000" when others;

end behavioral;

PORTE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity porte is

    Port ( txclk : in  STD_LOGIC;

           areset : in  STD_LOGIC;

           crs : in  STD_LOGIC;

           enable_bar : in  STD_LOGIC;

            link_bar: in std_logic;

           selected : in  STD_LOGIC;

           carrier : in  STD_LOGIC;

           collision : in  STD_LOGIC;

           jam : in  STD_LOGIC;

           txdata : in  STD_LOGIC;

           prescale : in  STD_LOGIC;

           rx_en : buffer  STD_LOGIC;

           tx_en : buffer  STD_LOGIC;

           activity : buffer STD_LOGIC;

           jabber_bar : buffer  STD_LOGIC;

           partition_bar : buffer  STD_LOGIC);

end porte;

architecture Behavioral of porte is

type states is (clear_state, idle_state,cwatch_state,ccount_state,pwait_state,phold_state,

                           pcwatch_state,wait_state);

  --attribute state_encoding of states:type is one_hot_one;

  signal state,newstate: states;

  signal crsdd,link_bardd,enable_bardd:std_logic; 

  signal  tx_eni,carpres,transmit,copyd,copyin,collisiond:std_logic;

  signal jabcnt:std_logic_vector(3 downto 0);

  signal jabberclr,jabberinc:std_logic;

  signal quietd:std_logic;

  signal cccnt:std_logic_vector(6 downto 0);

  signal cclimit,nocoldone:std_logic;

  signal nocolcnt:std_logic_vector(7 downto 0);

  signal ccclr,ccinc,nocolclr,nocolinc:std_logic;

  component rdff1 is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           d : in  STD_LOGIC;

           q : buffer  STD_LOGIC);

            end component;

  component ascount is

                        generic(countersize:integer:=2);

                                    Port ( clk : in  STD_LOGIC;

                                                areset : in  STD_LOGIC;

           sreset : in  STD_LOGIC;

           enable : in  STD_LOGIC;

                   count : buffer  STD_LOGIC_vector(countersize-1 downto 0));

            end component;

component psynch is

Port ( clk : in  STD_LOGIC;

           preset : in  STD_LOGIC;

           d : in  STD_LOGIC;

           q : buffer  STD_LOGIC);

   end component;

component rsynch is

Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           d : in  STD_LOGIC;

           q : buffer  STD _LOGIC);

end component;

begin

u0: rsynch port map(txclk,areset,crs,crsdd);

u1: psynch       port map(txclk,areset,link_bar,link_bardd);

u2: psynch       port map(txclk,areset,enable_bar,enable_bardd);

u3: rdff1          port map(txclk,areset,tx_eni,tx_en);

u4: rdff1          port map(txclk,areset,copyin,copyd);

u5: rdff1          port map(txclk,areset,collision,collisiond);

u6: ascount generic map (4) port map (txclk, areset, jabberclr,jabberinc, jabcnt);

u7: ascount generic map (7) port map (txclk, areset, ccclr, ccinc,cccnt);

u8: ascount generic map (8) port map (txclk, areset, nocolclr,nocolinc, nocolcnt);

carpres<= crsdd and not enable_bardd;

activity<= carpres and not link_bardd and jabber_bar and partition_bar;

rx_en<= not enable_bardd and not link_bardd and selected and collision;

tx_eni<= not enable_bardd and not link_bardd and jabber_bar and transmit;

copyin<= carrier and not selected;

transmit<= txdata and (copyd or collisiond);

jabber_bar<= not (jabcnt(3) and jabcnt(2));

jabberclr<= not carpres;

jabberinc<= carpres and prescale and jabber_bar;

quietd<= not copyd;

cclimit<= cccnt(6);

nocoldone<= nocolcnt(7) ;

---Partition State Machine

pI: process (state, carpres, collisiond, copyd, quietd,nocoldone, cclimit, enable_bardd)

   begin

            case (state) is

                        when CLEAR_STATE=>

                                                partition_bar <= '1';

                                                ccclr <= '1';

                                                ccinc <= '0';

                                                nocolclr <= '1';

                                                nocolinc <= '0';

                        if (enable_bardd = '1') then

                                    newstate<= CLEAR_STATE;

                        elsif (quietd ='1') then

                                    newstate <= IDLE_STATE;

                        else

                                    newstate <= CLEAR_STATE;

                        end if;

                        when IDLE_STATE=>

                                                partition_bar <= '1';

                                                ccclr <= '0';

                                                ccinc <= '0';

                                                nocolclr <= '1';

                                                nocolinc <= '0';

                        if (enable_bardd = '1') then

                                    newstate <= CLEAR_STATE;

                        elsif (carpres = '1') then

                                    newstate <= CWATCH_STATE;

                        else

                                    newstate <= IDLE_STATE;

end if;

                        when CWATCH_STATE=>

                                                partition_bar <= '1';

                                                ccclr <= '0';

                                                ccinc <= collisiond;

                                                nocolclr <= '0';

                                                nocolinc <= '1';

                                    if (enable_bardd = '1') then

                                                newstate <= CLEAR_STATE;

                                    elsif (collisiond = '1') then

                                                newstate <= CCOUNT_STATE;

                                    elsif (carpres = '0') then

                                                newstate <= IDLE_STATE;

                                                elsif (nocoldone = '1') then

                                                newstate <= CLEAR_STATE;

                                    else

                                                newstate <= CWATCH_STATE;

end if;

                        when CCOUNT_STATE=>

                                                partition_bar <= '1';

                                                ccclr <= '0';

                                                ccinc <= '0';

                                                nocolclr <= '1';

                                                nocolinc <= '0';

                        if (enable_bardd = '1') then

                                    newstate <= CLEAR_STATE;

                        elsif (cclimit = '1' ) then

                                    newstate <= PWAIT_STATE;

                                    elsif (carpres = '0' and quietd='1')then

                                    newstate <= IDLE_STATE;

                        else

                                    newstate <= CCOUNT_STATE;

end if;

                        when PWAIT_STATE=>

                                                partition_bar<='0';

ccclr <='0';

                                                ccinc <='0';

                                                nocolclr <= '1';

                                                nocolinc <= '0';

                        if (enable_bardd = '1') then

                                    newstate <= CLEAR_STATE;

                        elsif (carpres='0' and quietd='1')then

                                    newstate <= PHOLD_STATE;

                        else

                                    newstate <= PWAIT_STATE;

end if;

                        when PHOLD_STATE=>

                                                partition_bar <= '0';

                                                ccclr <= '0';

                                                ccinc <= '0';

                                                nocolclr <= '1';

                                                nocolinc <= '0';

                        if (enable_bardd = '1') then

                                    newstate <= CLEAR_STATE;

                        elsif (collisiond = '1' or copyd='1') then

                                    newstate <= PCWATCH_STATE;

                        else

                                    newstate <= PHOLD_STATE;

                        end if;

                        when PCWATCH_STATE=>

                                                partition_bar <= '0';

                                                ccclr <= '0';

                                                ccinc <= '0';

                                                nocolclr <= '0';

                                                nocolinc <= '1';

                        if (enable_bardd = '1') then

                                    newstate <= CLEAR_STATE;

                        elsif (carpres = '1') then

                                    newstate <= PWAIT_STATE;

                        elsif (quietd = '0') then

                                    newstate <= PHOLD_STATE;

                        elsif (nocoldone = '1' and copyd ='1') then

                                    newstate <= WAIT_STATE;

                        else

                                    newstate <= PCWATCH_STATE;

end if;

                        when WAIT_STATE=>

                                                partition_bar <= '0';

                                                ccclr <= '1';

                                                ccinc <= '0';

                                                nocolclr <= '1';

                                                nocolinc<= '0';

                        if (enable_bardd = '1') then

                                    newstate <= CLEAR_STATE;

                        elsif (carpres = '0' and quietd='1')then

                                    newstate <= IDLE_STATE;

                                    else

                                    newstate <= WAIT_STATE;

end if;

end case;

end process;

--State Flip-Flop for Synthesis

            plelk: process (txclk,areset)

                        begin

                                    if areset = '1' then

                                                            state <= clear_state;

                                    elsif (txclk'event and txclk ='1') then

                                                            state <= newstate;

end if;

end process;

end Behavioral;

PSYNCH

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity psynch is

    Port ( clk : in  STD_LOGIC;

           preset : in  STD_LOGIC;

           d : in  STD_LOGIC;

           q : buffer  STD_LOGIC);

end psynch;

architecture Behavioral of psynch is

signal temp: std_logic;

begin

process(preset,clk)

                                    begin

                                                if (preset='1') then

                                                  q<='1';

                                                elsif(clk'event and clk='1') then

                                                  temp<=d;

                                                  q<= temp;                                         

                                                  end if;

end process;               

end Behavioral;

RDFF1

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity rdff1 is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           d : in  STD_LOGIC;

           q : buffer STD_LOGIC);

end rdff1;

architecture Behavioral of rdff1 is

            begin

                        p1: process(reset,clk) begin

                                                if(reset='1') then

                                                            q<='0';

                                                elsif(clk'event and clk='1') then

                                                            q<=d;

end if;

end process;

end Behavioral;

RDFF12

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity rdff1 is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           d : in  STD_LOGIC;

           q : buffer STD_LOGIC);

end rdff1;

architecture Behavioral of rdff1 is

            begin

                        p1: process(reset,clk) begin

                                                if(reset='1') then

                                                            q<='0';

                                                elsif(clk'event and clk='1') then

                                                            q<=d;

end if;

end process;

end Behavioral;

RREG

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity rreg is

             generic (size:integer:=2);

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           load : in  STD_LOGIC;

           d : in  STD_LOGIC_vector(size-1 downto 0);

           q : buffer STD_LOGIC_vector(size-1 downto 0));

end rreg;

architecture Behavioral of rreg is

begin

process(reset,clk)

                                    begin

                                                if (reset='1') then

                                                  q<=(others=>'0');

                                                elsif(clk'event and clk='1') then

                                                  if load='1' then

                                                  q<= d;                                              

                                                  end if;

                                                  end if;

end process;   

end Behavioral;

RSYNCH

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity rsynch is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           d : in  STD_LOGIC;

           q : buffer  STD_LOGIC);

end rsynch;

architecture Behavioral of rsynch is

signal temp: std_logic;

begin

process(reset,clk)

                                    begin

                                                if (reset='1') then

                                                  q<='0';

                                                elsif(clk'event and clk='1') then

                                                  temp<=d;

                                                  q<= temp;                                                                                end if;

end process;               

end Behavioral;

SYMBMUX

library ieee;

use ieee.std_logic_1164.all;

--use basic.counters_pkg.all;

entity symbmux is

port(                            txclk: in std_logic;

                                    areset: in std_logic;

                                    symbolclr: in std_logic;

                                    symbolinc: in std_logic;

                                    switch1: in std_logic;

                                    switch2: in std_logic;

                                    switch3: in std_logic;

                                    symbol1: in std_logic_vector( 1 downto 0);

                                    symbol2: in std_logic_vector( 1 downto 0);

                                    symbol3: in std_logic_vector( 1 downto 0);

                                    dmuxout: in std_logic_vector( 5 downto 0);

                                    symbolend1:buffer std_logic;

                                    symbolend2:buffer std_logic;

                                    symbolend3:buffer std_logic;

                                    txd5:buffer std_logic;

                                    txd4:buffer std_logic;

                                    txd3:buffer std_logic;

                                    txd2:buffer std_logic;

                                    txd1:buffer std_logic;

                                    txd0:buffer std_logic);

end symbmux;

architecture behavior of symbmux is

-- signals

            signal clearcount: std_logic;

            signal symbolcount: std_logic_vector(2 downto 0);

            signal  sosb1, sosb2, sosb3, bad1, bad2, bad3, jam: std_logic_vector(1 downto 0);

            signal txd, muxout, smuxout: std_logic_vector(5 downto 0);

-- Constants

            constant plus : std_logic_vector(1 downto 0) := "10";

            constant zero : std_logic_vector(1 downto 0) := "00";

constant minus: std_logic_vector(1 downto 0):="01";

component      rdff12 is

generic(size:integer:=2);

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           d : in  STD_LOGIC_VECTOR (size-1 downto 0);

           q : buffer  STD_LOGIC_VECTOR (size-1 downto 0));

end component;

component ascount is

generic(countersize:integer:=2);

    Port ( clk : in  STD_LOGIC;

           areset : in  STD_LOGIC;

           sreset : in  STD_LOGIC;

           enable : in  STD_LOGIC;

           count : buffer  STD_LOGIC_vector(countersize-1 downto 0));

end component;

            begin

-- Components

p1: ascount generic map(CounterSize => 3)

port map (txclk, areset, clearcount,symbolinc,symbolcount);--symbol count

p2: rdff12 generic map (size => 6)

port map (txclk, areset, muxout, txd);

                                    txd5 <= txd(5);

                                    txd4 <= txd(4);

                                    txd3 <= txd(3);

                                    txd2 <= txd(2);

                                    txd1 <= txd(1);

                                    txd0 <= txd(0);

            symbolend1<= symbolcount(0) and not symbolcount(1) and symbolcount(2);

            symbolend2<= symbolcount(0) and not symbolcount(1) and not symbolcount(2);

            symbolend3<= symbolcount(0) and symbolcount(1) and not symbolcount(2);

            clearcount<= symbolend1 or symbolclr;

-- Special symbol mux

                                    with symbol1 select

                                                            smuxout(1 downto 0) <=

                                                            jam when "00",                                                                                                                        sosb1 when "01",                                                                                                                    bad1 when "10",

                                                            zero when others;

--Line 1 switch mux

                                                with switch1 select

                                                            muxout(1 downto 0) <=

                                                            smuxout(1 downto 0) when '0',

                                                            dmuxout(1 downto 0) when others;

--Special symbol mux (Line 2)

                                                with symbol2 select

                                                            smuxout(3 downto 2) <=

                                                            jam when "00",                                                                                                                        sosb2 when "01",

                                                            bad2 when "10",

                                                            zero when others;

-- Line 2 switch mux

                                                with switch2 select

                                                            muxout(3 downto 2) <=

                                                            smuxout(3 downto 2) when '0',

                                                            dmuxout (3 downto 2) when others;

--Special symbol mux (Line 3)

                                                with symbol3 select

                                                            smuxout(5 downto 4) <=

                                                            jam when "00",

                                                            sosb3 when "01",

                                                            bad3 when "10",

                                                            zero when others;

--Line 3 switch mux

                                                with switch3 select

                                                             muxout(5 downto 4) <=

                                                            smuxout(5 downto 4) when '0',

                                                            dmuxout(5 downto 4) when others;

--Jam/preamble generation (all lines)

                                    with symbolcount(0) select

                                    jam <=

plus when '0',

                                                            minus when others;

--SOSB generation (line 1)

                                    with symbolcount select

                                    sosb1 <=

                                                            plus when "000",

                                                            minus when "001",

                                                            plus when "010",

                                                            minus when "011",

                                                            minus when "100",

                                                            plus when "101",

                                                            zero when others;

--SOSB generation (line 2)

                                    with symbolcount select

                                    sosb2 <=

                                                            minus when "000",

                                                            plus when "001",

                                                            plus when "010",

                                                            minus when "011",

                                                            plus when "100",

                                                            minus when "101",

                                                            zero when others;

-- Sosb generation (line 3)

                                    with symbolcount select

                                    sosb3 <=

                                                            plus when "000",

                                                            minus when "001",

                                                            minus when "010",

                                                            plus when "011",

                                                            plus when "100",

                                                            minus when "101",

                                                            zero when others;

--bad code generation (1 ine 1)

                                    with symbolcount select

                                    bad1 <=

                                                            minus when "000",

                                                            minus when "001",

                                                            minus when "010",

                                                            plus when "011",

                                                            plus when "100",

                                                            plus when "101",

                                                            zero when others;

--Bad code generation (line 2)

   with symbolcount select

                                    bad2 <=

                                                            plus when "000",

                                                            plus when "001",

                                                            minus when "010",

                                                            minus when "011",

                                                            minus when "100",

                                                            plus when "101",

                                                            zero when others;

--code generation (line 3) 

                                    with symbolcount select

             bad3 <=

                                                            minus when "000",

                                                            plus when "001",

                                                            plus when "010",

                                                            plus when "011",

                                                            minus when "100",

                                                            minus when "101",

                                                            zero when others;

end behavioral ;

TOP

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

--library UNISIM;

--use UNISIM.VComponents.all;

entity top is

 port(

                                                reset :in std_logic;--Global reset

                                                clk : in std_logic; --to CKTPAD for TX_CLK

                                                rxd5 :in std_logic; --RXD5

                                                rxd4 :in std_logic; --RXD4

                                                rxd3 :in std_logic; --RXD3

                                                rxd2 :in std_logic; --RXD2

                                                rxd1 :in std_logic; --RXDI

                                                rxd0 :in std_logic;-- RXD0

                                                rx_dv :in std_logic; --RX_DV

                                                rx_er :in std_logic;-- RX_ER

                                                clk1 :in std_logic;-- RX_CLKI

                                                crs1 :in std_logic; --CRSI

                                                enable1_bar:in std_logic; --ENABLEI                      

                                                link1_bar :in std_logic; --LINKI

                                                clk2 :in std_logic; --RX_CLK2

                                                crs2: in std_logic;-- CRS2

                                                enable2_bar: in std_logic; --ENABLE2

                                                link2_bar: in std_logic; --LINK2

                                                clk3: in std_logic; --RXJLK3

                                                crs3 :in std_logic; --CRS3

                                                enable3_bar :in std_logic;-- ENABLE3

                                                link3_bar: in std_logic;-- LINK3

                                                clk4: in std_logiC; --RX_CLK4

                                                crs4 :in std_logic; --CRS4

                                                enable4_bar :in std_logic;-- ENABLE4

                                                link4_bar :in std_logic;-- LINK4

                                                clk5 :in std_logic; --RX_CLK5

                                                crs5: in std_logic;-- CRS5

                                                enable5_bar :in std_logic;-- ENABLE5

                                                link5_bar: in std_logic;-- LINK5

                                                clk6 :in std_logic; --RX_CLK6

                                                crs6 :in std_logic; --CRS6

                                                enable6_bar :in std_logic; --ENABLE6

                                                link6_bar: in std_logic; --LINK6

                                                clk7 : in std_logic;-- RX_CLK7

                                                crs7 :in std_logic; --CRS7

                                                enable7_bar:  in std_logic; --ENABLE7

                                                link7_bar : in std_logic; --LINK?

                                                clk8 :in std_logic; --RX_CLK8

                                                crs8 :in std_logic; --CRS8

                                                enable8_bar :in std_logic; --ENABLE8

                                                link8_bar: in std_logic; --LINK8

                                                rx_en1: buffer std_logic;-- RX_ENI

                                                tx_en1: buffer std_logic; --TX_ENI

                                                partition1_bar: buffer std_logic; --PARTITIONI

                                                jabber1_bar: buffer std_logic; --JABBERI

                                                rx_en2: buffer std_logic; --RX_EN2

                                                tx_en2: buffer std_logic; --TX_EN2

                                                partition2_bar: buffer std_logic;-- PARTITION2

                                                jabber2_bar: buffer std_logic; --JABBER2

                                                rx_en3 :buffer std_logic; --RX_EN3

                                                tx_en3 :buffer std_logic; --tX_EN3

                                                partition3_bar: buffer std_logic; --PARTITION 3

                                                jabber3_bar: buffer std_logic; --JABBER3

                                                rx_en4 :buffer std_logic; --RX_EN4

                                                tx_en4 :buffer std_logic; -- TX_EN4

                                                partition4_bar: buffer std_logic; --PARTITION4

                                                jabber4_bar: buffer std_logic; --JABBER4

                                                rx_en5: buffer std_logic; --RX_ENS

                                                tx_en5: buffer std_logic; --TX_ENS

                                                partition5_bar :buffer std_logic;-- PARTITIONS

                                                jabber5_bar :buffer std_logic; --JABBERS

                                                rx_en6 :buffer std_logic; --RX_EN6

                                                tx_en6 :buffer std_logic; --TX_EN6

                                                partition6_bar: buffer std_logic; --PARTITION6

                                                jabber6_bar: buffer std_logic; --JABBER6

                                                rx_en7 :buffer std_logic; --RX_EN7

                                                tx_en7 : buffer std_logic; --nCEN7

                                                partition7_bar : buffer std_logic; --PARTITION 7

                                                jabber7_bar: buffer std_logic; --JABBER7

                                                rx_en8 :buffer std_logic;-- RX_EN8

                                                tx_en8 :buffer std_logic; --TX_EN8

                                                partition8_bar: buffer std_logic; --PARTITION8

                                                jabber8_bar :buffer std_logic; --JABBER8

                                                txd5 :buffer std_logic;-- TXD5

                                                txd4 :buffer std_logic;-- TXD4

                                                txd3 :buffer std_logic;-- TXD3

                                                txd2 :buffer std_logic;-- TXD2

                                                txd1 :buffer std_logic;-- TXDl

                                                txd0 :buffer std_logic; --TXD0

                                                txdata :buffer std_logic; --TX_ENal

                                                idle :buffer std_logic; --Idle generation

                                                preamble :buffer std_logic; --Preamble generation

                                                data :buffer std_logic; --Data generation

                                                jam :buffer std_logic; --Jam generation

                                                collision :buffer std_logic; --Collision indication

                                                wptr2 :buffer std_LOgic; --Write pointer2

                                                wptr1 :buffer std_logic; --Write pointerl

                                                wptr0 :buffer std_LOgic; --Write pointer0

                                                rptr2 :buffer std_logic; --Read pointer2

                                                rptr1 :buffer std_logic; -- Read pointerl

                                                rptr0 : buffer std_logic ;--Read pointer0

                                                mux: buffer std_logic_vector(5 downto 0)

                                                );

end top;

architecture Behavioral of top is

component porte is

    Port ( txclk : in  STD_LOGIC;

           areset : in  STD_LOGIC;

           crs : in  STD_LOGIC;

           enable_bar : in  STD_LOGIC;

            link_bar: in std_logic;

           selected : in  STD_LOGIC;

           carrier : in  STD_LOGIC;

           collision : in  STD_LOGIC;

           jam : in  STD_LOGIC;

           txdata : in  STD_LOGIC;

           prescale : in  STD_LOGIC;

           rx_en : buffer  STD_LOGIC;

           tx_en : buffer  STD_LOGIC;

           activity : buffer STD_LOGIC;

           jabber_bar : buffer  STD_LOGIC;

           partition_bar : buffer  STD_LOGIC);

end component;

 component  clk_mux

Port (  clk1 : in  STD_LOGIC;

           clk2 : in  STD_LOGIC;

           clk3 : in  STD_LOGIC;

           clk4 : in  STD_LOGIC;

           clk5 : in  STD_LOGIC;

           clk6 : in  STD_LOGIC;

           clk7 : in  STD_LOGIC;

           clk8 : in  STD_LOGIC;

            clk9: in std_logic;

sel1 : in  STD_LOGIC;

           sel2 : in  STD_LOGIC;

           sel3 : in  STD_LOGIC;

           sel4 : in  STD_LOGIC;

           sel5 : in  STD_LOGIC;

           sel6 : in  STD_LOGIC;

           sel7 : in  STD_LOGIC;

           sel8 : in  STD_LOGIC;

            sel9 :in  std_logic;

           rxclk : buffer  STD_LOGIC);

            end component;

component fifo is

port (   rxclk: in std_logic; --from clock mux circuit

txclk: in std_logic; --Reference TX_CLK

            areset: in std_logic;-- Asynch reset                            

            wptrclr: in std_logic; --FIFO write pointer clear

            wptrinc: in std_logic; --FIFO write pointer incr

            rptrclr: in std_logic; --FIFO read pointer clear

            rptrinc: in std_logic; --FIFO read poi~ter incr

rxd5: in std_logic; --FIFO data input

            rxd4: in std_logic;-- FIFO data input

            rxd3: in std_logic;-- FIFO d~ta input

            rxd2: in std_logic;-- FIFO data input

            rxd1: in std_logic; --FIFO data input

            rxd0: in std_logic; ---FIFO data input

            dmuxout: buffer std_logic_vector(5 downto 0);

            ---FIFO mux output

            wptr2 :buffer std_logic;

            wptr1:buffer std_logic;

            wptr0:buffer std_logic;

            rptr2:buffer std_logic;

            rptr1:buffer std_logic;

            rptr0:buffer std_logic

            );

end component;         

component arbiter8 is

Port ( txclk : in  STD_LOGIC;

           areset : in  STD_LOGIC;

           activity1 : in  STD_LOGIC;

           activity2 : in  STD_LOGIC;

           activity3 : in  STD_LOGIC;

           activity4 : in  STD_LOGIC;

           activity5 : in  STD_LOGIC;

           activity6 : in  STD_LOGIC;

           activity7 : in  STD_LOGIC;

           activity8 : in  STD_LOGIC;

           sel1 : buffer  STD_LOGIC;

           sel2 : buffer STD_LOGIC;

           sel3 : buffer  STD_LOGIC;

           sel4 : buffer  STD_LOGIC;

           sel5 : buffer  STD_LOGIC;

           sel6 : buffer  STD_LOGIC;

           sel7 : buffer  STD_LOGIC;

           sel8 : buffer STD_LOGIC;

           nosel : buffer STD_LOGIC;

           carrier :buffer  STD_LOGIC;

           collision : buffer STD_LOGIC);

end component;

component symbmux is

port(   txclk: in std_logic;

areset: in std_logic;

            symbolclr: in std_logic;

            symbolinc: in std_logic;

            switch1: in std_logic;

            switch2: in std_logic;

            switch3: in std_logic;

            symbol1: in std_logic_vector( 1 downto 0);

            symbol2: in std_logic_vector( 1 downto 0);

            symbol3: in std_logic_vector( 1 downto 0);

            dmuxout: in std_logic_vector( 5 downto 0);

            symbolend1:buffer std_logic;

            symbolend2:buffer std_logic;

            symbolend3:buffer std_logic;

            txd5:buffer std_logic;

            txd4:buffer std_logic;

            txd3:buffer std_logic;

            txd2:buffer std_logic;

            txd1:buffer std_logic;

            txd0:buffer std_logic);

end component;

component      control is

port (   txclk: in std_logic;--Reference TX_CLK

areset: in std_logic;--Async reset

            carrier: in std_logic;

collision:in std_logic;

            rx_error: in std_logic;

         rx_dv:  in std_logic;

         symbolendl:in std_logic;

         symbolend2: in std_logic;

         symbolend3: in std_logic;

         symbolclr:  buffer std_logic;

         symbolinc:buffer std_logic;

         symbol1:buffer std_logic_vector(1 downto 0);

         symbol2:buffer std_logic_vector(1 downto 0);

            symbol3:buffer std_logic_vector(1 downto 0);

            switch1: buffer std_logic;

            switch2:buffer std_logic;

            switch3:buffer std_logic;

            wptrclr:buffer std_logic;

            wptrinc:buffer std_logic;

            rptrclr:buffer std_logic;

            rptrinc:buffer std_logic;

            txdata:buffer std_logic;

            idle:buffer std_logic;

            preamble:buffer std_logic;

            data:    buffer std_logic;                                

            col:  buffer std_logic;

            prescale:buffer std_logic);

end component;

signal txclk1, nosel, areset, sel1, sel2, sel3, sel4: std_logic;

signal sel5, sel6, sel7, sel8,sel9, rxclk, txclk: std_logic;

signal activity1, activity2, activity3, activity4: std_logic;

signal activity5, activity6, activity7, activity8: std_logic;

signal carrier: std_logic;

signal wptrclr, wptrinc, rptrclr, rptrinc,symbolinc:std_logic;

signal switch1, switch2, switch3: std_logic;

signal symbolend1, symbolend2, symbolend3: std_logic;

signal symbolclr : std_logic;

signal symbol1, symbol2 , symbol3: std_logic_vector(1 downto 0);

signal dmuxout: std_logic_vector(5 downto 0);

signal prescale: std_logic;

begin

--Components

ul:clk_mux  port map

( clk1, clk2, clk3, clk4, clk5, clk6, clk7, clk8, txclk, sel1, sel2, sel3, sel4, sel5, sel6, sel7, sel8,nosel,rxclk);

u2: arbiter8 port map

(txclk, areset ,activity1, activity2, activity3, activity4, activity5, activity6, activity7, activity8, sel1, sel2, sel3, sel4, sel5, sel6, sel7, sel8, nosel, carrier, collision);

u3: fifo port map

(rxclk, txclk, areset, wptrclr, wptrinc, rptrclr, rptrinc, rxd5, rxd4, rxd3, rxd2, rxd1, rxd0,dmuxout, wptr2, wptr1, wptr0, rptr2, rptr1, rptr0);

            u4: symbmux port map

                        (txclk, areset,symbolclr, symbolinc, switch1, switch2, switch3, symbol1,

symbol2, symbol3, dmuxout, symbolend1, symbolend2,symbolend3, txd5, txd4, txd3, txd2, txd1, txd0);

            u5: control port map

(txclk, areset, carrier, collision, rx_er, rx_dv,symbolend1, symbolend2, symbolend3, symbolclr, symbolinc, symbol1, symbol2, symbol3, switch1, switch2, switch3,wptrclr, wptrinc, rptrclr, rptrinc, txdata, idle, preamble, data, jam, prescale);

u6: porte port map

(txclk, areset,crs1, enable1_bar, link1_bar,sel1, carrier, collision, jam, txdata, prescale, rx_en1,  tx_en1,activity1, jabber1_bar, partition1_bar);

            u7: porte port map

(txclk, areset,crs2, enable2_bar, link2_bar,sel2, carrier, collision, jam, txdata, prescale, rx_en2, tx_en2,activity2, jabber2_bar, partition2_bar);

            u8: porte port map

(txclk, areset,crs3, enable3_bar, link3_bar,sel3, carrier, collision, jam, txdata, prescale, rx_en3, tx_en3,activity3, jabber3_bar, partition3_bar);

            u9: porte port map

(txclk, areset,crs4, enable4_bar, link4_bar,sel4, carrier, collision, jam, txdata, prescale, rx_en4, tx_en4,activity4, jabber4_bar, partition4_bar);

            u10: porte port map

(txclk, areset,crs5, enable5_bar, link5_bar,sel5, carrier, collision, jam, txdata,          prescale, rx_en5, tx_en5,activity5, jabber5_bar, partition5_bar);

            ull: porte port map

(txclk, areset, crs6, enable6_bar, link6_bar,sel6, carrier, collision, jam, txdata, prescale, rx_en6, tx_en6,activity6, jabber6_bar, partition6_bar);

            u12: porte port map

(txclk, areset,crs7, enable7_bar, link7_bar,sel7, carrier, collision, jam, txdata, prescale, rx_en7, tx_en7,activity7, jabber7_bar, partition7_bar)

u13: porte port map

(txclk, areset,crs8, enable8_bar, link8_bar,sel8, carrier, collision, jam, txdata, prescale, rx_en8, tx_en8,activity8, jabber8_bar, partition8_bar);

txclk <= clk;

txclk1<= clk;

areset <= reset;

 mux<=dmuxout;

end behavioral;

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